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| data sheet mos integrated circuit m pd750004,750006,750008,750004(a),750006(a),750008(a) 4 bit single-chip microcontroller the m pd750008 is one of the 75xl series 4-bit single-chip microcontrollers, which provide data processing capability equal to that of an 8-bit microcontroller. the m pd750008 is an advanced model of the m pd75008. it features an enhanced cpu function and enables high- speed operation at a low voltage of 2.2 v. it can be substituted for the m pd75008. in addition, it is best suited to applications using batteries. the m pd750008(a) has a higher reliability than the m pd750008. a built-in one-time prom product, m pd75p0016, is also available. it is suitable for small-scale production and evaluation of application systems. the following users manual describes the details of the functions of the m pd750008. be sure to read it before designing application systems. m pd750008 users manual: u10740e features ? capable of low-voltage operation: v dd = 2.2 to 5.5 v ? internal memory program memory (rom) : 4096 8 bits ( m pd750004 and m pd750004(a)) : 6144 8 bits ( m pd750006 and m pd750006(a)) : 8192 8 bits ( m pd750008 and m pd750008(a)) data memory (ram) : 512 4 bits applications ? m pd750004, m pd750006, and m pd750008 cordless telephones, radio devices, audio products, and home electric appliances ? m pd750004(a), m pd750006(a), and m pd750008(a) electrical equipment for automobiles the m pd750004, m pd750006, m pd750008, m pd750004(a), m pd750006(a), and m pd750008(a) differ only in quality grade. in this manual, the m pd750008 is described unless otherwise specified. users of other than the m pd750008 should read m pd750008 as referring to the pertinent product. when the description differs among m pd750004, m pd750006, and m pd750008, they also refer to the pertinent (a) products. m pd750004 ? m pd750004(a), m pd750006 ? m pd750006(a), m pd750008 ? m pd750008(a) the information in this document is subject to change without notice. 1990 the mark shows major revised points. ? function for specifying the instruction execution time (useful for high-speed operation and saving power) 0.95 m s, 1.91 m s, 3.81 m s, 15.3 m s (when operating at 4.19 mhz) 0.67 m s, 1.33 m s, 2.67 m s, 10.7 m s (when operating at 6.0 mhz) 122 m s (when operating at 32.768 khz) ? enhanced timer function (4 channels) ? can be easily substituted for the m pd75008 because this product succeeds to the functions and instructions of the m pd75008. 1994 document no. u10738ej3v0ds00 (3rd edition) date published february 1997 j printed in japan
2 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) ordering information part number package quality grade m pd750004cu- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) standard m pd750004gb- -3bs-mtx 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) standard m pd750006cu- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) standard m pd750006gb- -3bs-mtx 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) standard m pd750008cu- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) standard m pd750008gb- -3bs-mtx 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) standard m pd750004cu(a)- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) special m pd750004gb(a)- -3bs-mtx 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) special m pd750006cu(a)- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) special m pd750006gb(a)- -3bs-mtx 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) special m pd750008cu(a)- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) special m pd750008gb(a)- -3bs-mtx 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) special remark is a mask rom code number. differences between m pd75000 and m pd75000 (a) product number item quality grade standard special please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. m pd750004 m pd750006 m pd750008 m pd750004(a) m pd750006(a) m pd750008(a) 3 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) rom ram functions cmos input cmos i/o n-ch open drain i/o total 8 18 8 34 can incorporate 7 pull-up resistors that are specified with the software. can directly drive the led. can incorporate 18 pull-up resistors that are specified with the software. can directly drive the led. can withstand 13 v. can incorporate pull-up resistors that are specified with the mask option. serial interface clock output (pcl) buzzer output (buz) vectored interrupt test input system clock oscillator standby operating ambient temperature range supply voltage package item command execution time internal memory general-purpose register i/o port timer bit sequential buffer (bsb) 4 channels ? 8-bit timer/event counter: 1 channel ? 8-bit timer counter: 1 channel ? basic interval timer/watchdog timer: 1 channel ? lock timer: 1 channel ? three-wire serial i/o mode ... switchable between the start lsb and the start msb ? two-wire serial i/o mode ? sbi mode 16 bits ? f , 524 khz, 262 khz, 65.5 khz (when the main system clock operates at 4.19 mhz) ? f , 750 khz, 375 khz, 93.8 khz (when the main system clock operates at 6.0 mhz) ? 2 khz, 4 khz, 32 khz (when the main system clock operates at 4.19 mhz or when the subsystem clock operates at 32.768 khz) ? 2.93 khz, 5.86 khz, 46.9 khz (when the main system clock operates at 6.0 mhz) external : 3 internal : 4 external : 1 internal : 1 ? ceramic or crystal oscillator for main system clock ? crystal oscillator for subsystem clock stop/halt mode t a = -40 to +85 c v dd = 2.2 to 5.5 v 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) function ? 0.95, 1.91, 3.81, 15.3 m s (when the main system clock operates at 4.19 mhz) ? 0.67, 1.33, 2.67, 10.7 m s (when the main system clock operates at 6.0 mhz) ? 122 m s (when the subsystem clock operates at 32.768 khz) 4096 8 bits ( m pd750004) 6144 8 bits ( m pd750006) 8192 8 bits ( m pd750008) 512 4 bits ? when operating in 4 bits: 8 4 banks ? when operating in 8 bits: 4 4 banks 4 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) contents 1. pin configuration (top view) ......................................................................................... 6 2. block diagram ...................................................................................................................... 8 3. pin functions ......................................................................................................................... 9 3.1 port pins ...................................................................................................................................... 9 3.2 non-port pins ............................................................................................................................ 10 3.3 pin input/output circuits ..................................................................................................... 11 3.4 connection of unused pins ................................................................................................ 13 4. mk i mode/mk ii mode switch function ........................................................................ 14 4.1 differences between mk i mode and mk ii mode ........................................................ 14 4.2 setting of the stack bank selection register (sbs) ............................................ 15 5. memory configuration ..................................................................................................... 16 6. peripheral hardware functions ................................................................................ 21 6.1 digital i/o ports ....................................................................................................................... 21 6.2 clock generator .................................................................................................................... 21 6.3 control functions of subsystem clock oscillator ............................................ 23 6.4 clock output circuit ............................................................................................................ 24 6.5 basic interval timer/watchdog timer ........................................................................... 25 6.6 clock timer ................................................................................................................................ 26 6.7 timer/event counter .............................................................................................................. 27 6.8 serial interface ...................................................................................................................... 30 6.9 bit sequential buffer ........................................................................................................... 32 7. interrupt functions and test functions ................................................................ 33 8. standby function ................................................................................................................ 35 9. reset function ..................................................................................................................... 36 10. mask option ........................................................................................................................... 39 11. instruction set .................................................................................................................... 40 12. electrical characteristics .......................................................................................... 53 13. characteristic curve (reference values) ............................................................. 67 5 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 14. package drawings .............................................................................................................. 70 15. recommended soldering conditions ......................................................................... 73 appendix a functions of the m pd75008, m pd750008, and m pd75p0016 ...................... 74 appendix b development tools .......................................................................................... 76 appendix c related documents .......................................................................................... 80 6 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 1. pin configuration (top view) ? 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m pd750004cu- , m pd750004cu(a)- m pd750006cu- , m pd750006cu(a)- m pd750008cu- , m pd750008cu(a)- ic : internally connected (connect directly to v dd .) v ss p40 p41 p42 p43 p50 p51 p52 p53 p60/kr0 p61/kr1 p62/kr2 p63/kr3 p70/kr4 p71/kr5 p72/kr6 p73/kr7 p20/pto0 p21/pto1 p22/pcl p23/buz xt1 xt2 reset x1 x2 p33 p32 p31 p30 p81 p80 p03/si/sb1 p02/so/sb0 p01/sck p00/int4 p13/ti0 p12/int2 p11/int1 p10/int0 ic v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 7 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) ? 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) m pd750004gb- -3bs-mtx, m pd750004gb(a)- -3bs-mtx m pd750006gb- -3bs-mtx, m pd750006gb(a)- -3bs-mtx m pd750008gb- -3bs-mtx, m pd750008gb(a)- -3bs-mtx ic : internally connected (connect directly to v dd .) pin names p00 - 03 : port 0 so : serial output p10 - 13 : port 1 sb0, sb1 : serial data bus 0, 1 p20 - 23 : port 2 reset : reset p30 - 33 : port 3 ti0 : timer input 0 p40 - 43 : port 4 pto0, pto1 : programmable timer output 0, 1 p50 - 53 : port 5 buz : buzzer clock p60 - 63 : port 6 pcl : programmable clock p70 - 73 : port 7 int0, 1, 4 : external vectored interrupt 0, 1, 4 p80, 81 : port 8 int2 : external test input 2 kr0 - kr7 : key return 0 - 7 x1, x2 : main system clock oscillation 1, 2 sck : serial clock xt1, xt2 : subsystem clock oscillation 1, 2 si : serial input nc : no connection ic : internally connected p13/ti0 p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p80 p81 p30 p31 p32 p33 p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 p60/kr0 p53 p52 p51 p50 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 nc p43 p42 p41 p40 v ss xt1 xt2 reset x1 x2 p73/kr7 p20/pto0 p21/pto1 p22/pcl p23/buz v dd ic p10/int0 p11/int1 p12/int2 nc 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 8 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 2. block diagram note the rom capacity depends on the product. bit seq. buffer (16) port 0 p00 - p03 4 port 1 port 2 4 port 3 p30 - p33 4 port 4 p40 - p43 4 port 5 p50 - p53 4 port 6 p60 - p63 4 v ss v dd reset ic cpu clock f stand by control x2 x1 xt2 xt1 system clock generator main sub clock divider clock output control fx/2 n pcl/p22 general register data memory (ram) 512 4 bits bank sbs sp (8) cy alu program counter program memory note (rom) decode and control basic interval timer/ watchdog timer ti0/p13 intbt 8-bit timer/event counter #0 pto0/p20 intt0 tout0 8-bit timer counter #1 intt1 tout0 clocked serial interface si/sb1/p03 interrupt control int0/p10 so/sb0/p02 sck/p01 int1/p11 int2/p12 int4/p00 kr0/p60- kr7/p73 watch timer 8 port 7 p70 - p73 4 port 8 p80, p81 2 p10 - p13 4 p20 - p23 pto1/p21 intcsi intw buz/p23 9 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 3. pin functions 3.1 port pins notes 1. the circle ( ) indicates the schmitt trigger input. 2. when pull-up resistors that can be specified with the mask option are not incorporated (when pins are used as n-ch open-drain input ports), the input leak low current increases when an input instruction or bit operation instruction is executed. i/o circuit type note 1 -a -b -c -c e-b e-b m-d m-d -a -a e-b when reset input input input input high level (when pull-up resistors are provided) or high impedance high level (when pull-up resistors are provided) or high impedance input input input 8-bit i/o function 4-bit input port (port0). for p01 - p03, built-in pull-up resistors can be connected by software in units of 3 bits. 4-bit input port (port1). built-in pull-up resistors can be connected by software in units of 4 bits. a noise eliminator can be selected only when the p10/int0 pin is used. 4-bit i/o port (port2). built-in pull-up resistors can be connected by software in units of 4 bits. programmable 4-bit i/o port (port3). i/o can be specified bit by bit. built-in pull-up resistors can be connected by software in units of 4 bits. n-ch open-drain 4-bit i/o port (port4). a pull-up resistor can be provided bit by bit (mask option). withstand voltage is 13 v in open-drain mode. n-ch open-drain 4-bit i/o port (port5). a pull-up resistor can be provided bit by bit (mask option). withstand voltage is 13 v in open-drain mode. programmable 4-bit i/o port (port6). i/o can be specified bit by bit. built-in pull-up resistors can be connected by software in units of 4 bits. 4-bit i/o port (port7). built-in pull-up resistors can be connected by software in units of 4 bits. 2-bit i/o port (port8). built-in pull-up resistors can be connected by software in units of 2 bits. b f f m b pin name p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 - p33 p40 - p43 notes 2 p50 - p53 notes 2 p60 p61 p62 p63 p70 p71 p72 p73 p80 p81 input/ output input i/o i/o i/o input i/o i/o i/o i/o i/o i/o i/o f f shared pin int4 sck so/sb0 si/sb1 int0 int1 int2 ti0 pto0 pto1 pcl buz - - - kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 - - 10 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 3.2 non-port pins notes 1. the circle ( ) indicates the schmitt trigger input. 2. with a noise eliminator/asynchronously selectable 3. asynchronous b b f f m b function inputs external event pulse to the timer/event counter timer/event counter output timer counter output clock output arbitrary frequency output (for buzzer output or system clock trimming) serial clock i/o serial data output serial data bus i/o serial data input serial data bus i/o edge detection vectored interrupt input (both rising and falling edges are detected) rising edge detection testable input falling edge detection testable input falling edge detection testable input crystal/ceramic connection pin for main system clock generation. when external clock signal is used, it is applied to x1, and its reverse phase signal is applied to x2. crystal connection pin for subsystem clock generation. when external clock signal is used, it is applied to xt1, and it reverse phase signal is applied to xt2. xt1 can be used as a 1-bit input (test). system reset input (active low) internally connected. (to be connected directly to v dd ) positive power supply ground potential input/ output input output i/o input input input i/o i/o input - input - input - - - when reset input input input input input input - - - - - - edge detection vectored interrupt input (detection edge selectable). a noise eliminator can be selected when int0/p10 is used. shared pin p13 p20 p21 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60 - p63 p70 - p73 - - - - - - note 3 note 2 note 3 i/o circuit type note 1 -c e-b -a -b -c -c -a -a - - - - - b pin name ti0 pto0 pto1 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0 - kr3 kr4 - kr7 x1 x2 xt1 xt2 reset ic v dd v ss f f 11 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 3.3 pin input/output circuits the input/output circuit of each m pd750008 pin is shown below in a simplified manner. type a type d type b type e-b type b-c type f-a schmitt trigger input with hysteresis in p.u.r.: pull-up resistor in p-ch p.u.r. enable p.u.r. v dd p.u.r.: pull-up resistor p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type a p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type b p.u.r.: pull-up resistor push-pull output which can be set to high-impedance output (off for both p-ch and n-ch) v dd p-ch n-ch out data output disable cmos input buffer v dd in p-ch n-ch 12 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) type f-b type m-c type m-d p.u.r.: pull-up resistor v dd p-ch n-ch in/out v dd p-ch p.u.r. p.u.r. enable output disable (p) data output disable output disable (n) p.u.r.: pull-up resistor n-ch p.u.r. data output disable p.u.r. enable v dd p-ch in/out p.u.r.: pull-up resistor n-ch (withstand voltage: +13 v) in/out data v dd output disable p.u.r. (mask option) note p.u.r note v dd p-ch input instruction pull-up resistor that operates only when pull-up resistors that can be specified with the mask option are not incorporated and an input instruction is executed. (when the pin is low, the current flows from v dd to the pin.) voltage restriction circuit (withstand voltage: +13 v) 13 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) input state : to be connected to v ss or v dd through a separate resistor output state : to be left open input state : to be connected to v ss or v dd through a separate resistor output state : to be left open input state : to be connected to v ss output state : to be connected to v ss (do not connect to a pull-up resistor specified with a mask option.) 3.4 connection of unused pins table 3-1 connection of unused pins note when the subsystem clock is not used, set sos.0 to 1 (not to use the built- in feedback resistor). pin name recommended connection p00/int4 to be connected to v ss or v dd p01/sck p02/so/sb0 p03/si/sb1 to be connected to v ss p10/int0 - p12/int2 to be connected to v ss or v dd p13/ti0 p20/pto0 p21/pto1 p22/pcl p23/buz p30 - p33 p40 - p43 p50 - p53 p60/kr0 - p63/kr3 p70/kr4 - p73/kr7 p80, p81 xt1 note to be connected to v ss xt2 note to be left open ic to be connected directly to v dd to be connected to v ss or v dd through a separate resistor 14 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 4. mk i mode/mk ii mode switch function 4.1 differences between mk i mode and mk ii mode the cpu of the m pd750008 has two modes (mk i mode and mk ii mode) and which mode is used is selectable. bit 3 of the stack bank selection register (sbs) determines the mode. ? mk i mode: this mode has the upward compatibility with the m pd75008. it can be used in the 75xl cpus having a rom of up to 16 kb. ? mk ii mode: this mode is not compatible with the m pd75008. it can be used in all 75xl cpus, including those having a rom of 16 kb or more. table 4-1 shows the differences between mk i mode and mk ii mode. table 4-1 differences between mk i mode and mk ii mode caution mk ii mode can be used to support a program area larger than 16k bytes in the 75x series or 75xl series. this mode enhances a software compatibility with products whose program area is larger than 16k bytes. in mk ii mode, one more stack byte is required for execution of subroutine call instructions per stack compared with mk i mode. when a call !addr or callf !faddr instruction is executed, it takes one more machine cycle. therefore, mk i mode should be used for applications for which ram efficiency or processing capabilities is more critical than a software compatibility. number of stack bytes in a subroutine instruction bra !addr1 instruction calla !addr1 instruction call !addr instruction callf !faddr instruction 2 bytes none 3 machine cycles 2 machine cycles 3 bytes available 4 machine cycles 3 machine cycles mk i mode mk ii mode 15 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 4.2 setting of the stack bank selection register (sbs) the mk i mode and mk ii mode are switched by stack bank selection register. fig. 4-1 shows the register configuration. the stack bank selection register is set with a 4-bit memory operation instruction. to use the cpu in mk i mode, initialize the register to 100 b note at the beginning of the program. to use the cpu in mk ii mode, initialize it to 000 b note . note specify the desired value in . fig. 4-1 stack bank selection register format caution the cpu operates in mk i mode after the reset signal is issued, because bit 3 of sbs is set to 1. set bit 3 of sbs to 0 (mk ii mode) to use the cpu in mk ii mode. sbs0 sbs1 sbs2 sbs3 0 1 2 3 f84h address sbs symbol 0 0 0 1 memory bank 0 memory bank 1 other settings are inhibited. 0 1 mk ii mode mk i mode mode switching designation bit 2 must be set to 0. stack area designation 0 16 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 5. memory configuration ? program memory (rom) : 4096 8 bits (0000h-0fffh): m pd750004 6144 8 bits (0000h-17ffh): m pd750006 8192 8 bits (0000h-1fffh): m pd750008 ? 0000h to 0001h vector address table for holding the rbe and mbe values and program start address when a reset signal is issued (allowing a reset start at an arbitrary address) ? 0002h to 000dh vector address table for holding the rbe and mbe values and program start address for each vectored interrupt (allowing interrupt processing to be started at an arbitrary address) ? 0020h to 007fh table area referenced by the geti instruction ? data memory (ram) ? data area : 512 4 bits (000h to 1ffh) ? peripheral hardware area: 128 4 bits (f80h to fffh) 17 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 5-1 program memory map (in m pd750004) note can be used only in the mk ii mode. remark in addition to the above, the br pcde and br pcxa instructions can cause a branch to an address with only the 8 low-order bits of the pc changed. 000h address 7654 mbe rbe 0 0 internal reset start address (high-order 4 bits) 0 002h mbe rbe 0 0 intbt/int4 (high-order 4 bits) start address 004h mbe rbe 0 0 int0 (high-order 4 bits) start address 006h mbe rbe 0 0 int1 (high-order 4 bits) start address 008h mbe rbe 0 0 intcsi (high-order 4 bits) start address 00ah mbe rbe 0 0 intt0 (high-order 4 bits) start address 00ch mbe rbe 0 0 intt1 (high-order 4 bits) start address 020h 07fh 080h 7ffh 800h fffh geti instruction reference table (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf ! faddr instruction entry address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction call !addr instruction subroutine entry address br $addr instruction relative branch address brcb !caddr instruction branch address -15 to -1, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed internal reset start address intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address intt1 start address 18 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 5-2 program memory map (in m pd750006) note can be used only in the mk ii mode. remark in addition to the above, the br pcde and br pcxa instructions can cause a branch to an address with only the 8 low-order bits of the pc changed. 0000h address 0002h mbe rbe 0 intbt/int4 (high-order 5 bits) start address 0004h mbe rbe 0 int0 (high-order 5 bits) start address 0006h mbe rbe 0 int1 (high-order 5 bits) start address 0008h mbe rbe 0 intcsi (high-order 5 bits) start address 000ah mbe rbe 0 intt0 (high-order 5 bits) start address 0020h 007fh 0080h 07ffh 0800h mbe rbe 0 internal reset start address (high-order 5 bits) 0fffh 1000h 17ffh geti instruction reference table 000ch mbe rbe 0 intt1 (high-order 5 bits) start address (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf !faddr instruction entry address brcb !caddr instruction branch address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction call !addr instruction subroutine entry address br $addr instruction relative branch address -15 to -1, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed brcb !caddr instruction branch address 765 0 internal reset start address intbt/int4 int0 int1 intcsi intt0 intt1 start address start address start address start address start address start address 19 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 5-3 program memory map (in m pd750008) note can be used only in the mk ii mode. remark in addition to the above, the br pcde and br pcxa instructions can cause a branch to an address with only the 8 low-order bits of the pc changed. 0000h address 0002h mbe rbe 0 intbt/int4 (high-order 5 bits) start address 0004h mbe rbe 0 int0 (high-order 5 bits) start address 0006h mbe rbe 0 int1 (high-order 5 bits) start address 0008h mbe rbe 0 intcsi (high-order 5 bits) start address 000ah mbe rbe 0 intt0 (high-order 5 bits) start address 0020h 007fh 0080h 07ffh 0800h mbe rbe 0 internal reset start address (high-order 5 bits) 0fffh 1000h 1fffh geti instruction reference table 000ch mbe rbe 0 intt1 (high-order 5 bits) start address (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf !faddr instruction entry address brcb !caddr instruction branch address branch address of br bcxa, br bcde, br !addr, bra !addr1 or calla !addr1 note instruction call !addr instruction subroutine entry address br $addr instruction relative branch address -15 to -1, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed brcb !caddr instruction branch address 765 0 internal reset start address intbt/int4 int0 int1 intcsi intt0 intt1 start address start address start address start address start address start address 20 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 5-4 data memory map note memory bank 0 or 1 can be selected as the stack area. (32 4) data memory 000h 01fh 020h 0ffh 100h 1ffh f80h fffh 256 4 (224 4) 256 4 128 4 0 1 15 stack area note area for general-purpose register data area static ram (512 4) peripheral hardware area not contained memory bank 21 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) when the serial interface function is used, dual-function pins function as output pins in some operation modes. 4-bit input port allows input or output mode setting in units of 4 bits. allows input or output mode setting in units of 1 bit. operation and feature port name port0 port1 port2 port3 port4 port5 port6 port7 port8 6. peripheral hardware functions 6.1 digital i/o ports the m pd750008 has the following three types of i/o port: ? 8 cmos input pins (port0 and port1) ? 18 cmos i/o pins (port2, port3, and port6 to port8) ? 8 n-ch open-drain i/o pins (port4 and port5) total: 34 pins table 6-1 digital ports and their features 6.2 clock generator the clock generator generates clocks which are supplied to the peripheral hardware in the cpu. fig. 6-1 shows the configuration of the clock generator. operation of the clock generator is specified by the processor clock control register (pcc) and system clock control register (scc). the main system clock and subsystem clock are used. the instruction execution time can be made variable. ? 0.95 m s, 1.91 m s, 3.81 m s, 15.3 m s (when the main system clock is at 4.19 mhz) ? 0.67 m s, 1.33 m s, 2.67 m s, 10.7 m s (when the main system clock is at 6.0 mhz) ? 122 m s (when the subsystem clock is at 32.768 khz) allows input or output mode setting in units of 4 bits. whether to use pull-up resistors can be specified bit by bit with the mask option. allows input or output mode setting in units of 1 bit. allows input or output mode setting in units of 4 bits. ports 4 and 5 can be paired, allowing data i/o in units of 8 bits. ports 6 and 7 can be paired, allowing data i/o in units of 8 bits. 4-bit input 4-bit i/o 4-bit i/o (n-ch open-drain can withstand 13 v) 4-bit i/o 2-bit i/o also used as int4, sck, so/sb0, or si/sb1. also used as int0, inti, int2 or ti0. also used as pto0, pto1, pcl, or buz. - also used as one of kr0 to kr3. also used as one of kr4 to kr7. - allows input or output mode setting in units of 2 bits. function remarks 22 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 6-1 clock generator block diagram note instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. one clock cycle (t cy ) of the cpu clock ( f ) is equal to one machine cycle of an instruction. subsystem clock generator main system clock generator clock timer basic interval timer (bt) timer/event counter timer counter serial interface clock timer int0 noise eliminator clock output circuit 1/1 to 1/4096 frequency divider selec- tor selec- tor frequency divider f oscillator disable signal internal bus halt note stop note pcc2, pcc3 clear signal wait release signal from bt standby release signal from interrupt control circuit reset signal xt1 xt2 x1 x2 4 scc scc3 scc0 pcc pcc0 pcc1 pcc2 pcc3 stop flip-flop qs r halt flip-flop s q r f xt f x 1/2 1/16 1/4 1/4 wm.3 cpu int0 noise eliminator clock output circuit ? ? ? ? ? 23 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 6.3 control functions of subsystem clock oscillator the subsystem clock oscillator of the m pd750008 subseries has two control functions to decrease the supply current. ? the function to select with the software whether to use the built-in feedback resistor note ? the function to suppress the supply current by reducing the drive current of the built-in inverter when the supply voltage is high (v dd 3 2.7 v) note when the subsystem clock is not used, set sos.0 to 1 (not to use the built-in feedback resistor), connect xt1 to v ss , and open xt2. this makes it possible to reduce the supply current required by the subsystem clock oscillator. each function can be used by switching bits 0 and 1 in the sub-oscillator control register (sos). (see fig. 6-2. ) fig. 6-2 subsystem clock oscillator sos.0 sos.1 xt1 xt2 inverter feedback resistor v dd 24 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 6.4 clock output circuit the clock output circuit outputs a clock pulse from the p22/pcl pin. this clock pulse is used for remote control waveform output, peripheral lsis, etc. ? clock output (pcl): f , 524, 262, or 65.5 khz (at 4.19 mhz) f , 750, 375, or 93.8 khz (at 6.0 mhz) fig. 6-3 clock output circuit configuration remark measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable. from the clock generator clom selector output buffer port 2 input/ output mode specification bit p22 output latch pcl/p22 internal bus 4 port2.2 bit 2 of pmgb clom0 clom1 0 clom3 f f x /2 3 f x /2 4 f x /2 6 25 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 6.5 basic interval timer/watchdog timer the basic interval timer/watchdog timer has these functions: ? interval timer operation which generates a reference timer interrupt ? operation as a watchdog timer for detecting program crashes and resetting the cpu ? selection of wait time for releasing the standby mode and counting the wait time ? reading out the count value fig. 6-4 block diagram of the basic interval timer/watchdog timer note instruction execution from the clock generator internal bus 4 f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx basic interval timer (8-bit frequency divider) clear signal clear signal bt interrupt request flag vectored interrupt request signal irqbt wait release signal for standby release set signal bt 8 btm3 btm2 btm1 btm0 btm set1 note 3 1 wdtm internal reset signal set1 note 26 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 6.6 clock timer the m pd750008 contains one channel for a clock timer. the clock timer provides the following functions: ? sets the test flag (irqw) with a 0.5 sec interval. the standby mode can be released by irqw. ? the 0.5 second interval can be generated from either the main system clock (4.194304 mhz) or subsystem clock (32.768 khz). ? the time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. this is convenient for program debugging, testing, etc. ? any of the frequencies 2.048 khz, 4.096 khz, and 32.768 khz can be output to the p23/buz pin. this can be used for beep and system clock frequency trimming. ? the frequency divider circuit can be cleared so that a zero-second start of the clock can be made. fig. 6-5 clock timer block diagram ( ) is for f x = 4.194304 mhz, f xt = 32.768 khz. p23/buz internal bus 8 selector from the clock generator f x 128 (32.768 khz) f xt (32.768 khz) selector frequency divider selector intw irqw set signal 2 hz 0.5 sec wm7 0 wm5 wm4 wm3 wm2 wm1 wm0 p23 output latch bit 2 of pmgb port2.3 output buffer clear f w (32.768 khz) bit test instruction port 2 input/ output mode wm (4 khz) (2 khz) f w 2 7 (256 hz: 3.91 ms) f w 2 14 f w 2 3 f w 2 4 27 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 6.7 timer/event counter the m pd750008 contains one channel for a timer/event counter and one channel for a timer counter. figs. 6-6 and 6-7 show their configurations. the timer/event counter provides the following functions: ? programmable interval timer operation ? outputs square-wave signal of an arbitrary frequency to the pton pin (n = 0, 1) ? event counter operation (channel 0 only) ? divides the ti0 pin input by n and outputs to the pto0 pin (frequency divider operation) (channel 0 only) ? supplies serial shift clock to the serial interface circuit (channel 0 only) ? count read function 28 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 6-6 timer/event counter block diagram count register (8) ti0/p13 mpx timer operation start signal 8 8 8 from the clock generator internal bus tm06 tm05 tm04 tm03 tm02 port input buffer comparator (8) modulo register (8) t0 enable flag p20 output latch signal port 2 input/ output mode clear signal t0 tmod0 bit 2 of pmgb pto0/p20 output buffer reset reset irqt0 clear signal tout flip-flop tm0 input buffer irqt0 set signal intt0 port2.0 tout0 to serial interface cp match 8 8 toe0 set1 note f x /2 4 f x /2 6 f x /2 8 f x /2 10 note instruction execution 29 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 6-7 timer counter block diagram count register (8) mpx timer operation start signal ? ? ? 8 8 8 0 from the clock generator internal bus tm16 tm15 tm14 tm13 tm12 comparator (8) modulo register (8) t1 enable flag p21 output latch port 2 input/ output mode clear signal t1 tmod1 bit 2 of pmgb pto1/p21 output buffer reset reset irqt1 clear signal tout flip-flop tm1 set1 note irqt1 set signal intt1 port2.1 toe1 cp match 8 8 f x /2 6 f x /2 8 f x /2 10 f x /2 12 note instruction execution 30 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 6.8 serial interface m pd750008 has an 8-bit synchronous serial interface. the serial interface has the following four types of mode. ? operation stop mode ? three-wire serial i/o mode ? two-wire serial i/o mode ? sbi mode 31 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 6-8 serial interface block diagram internal bus 8 8 8 8/4 p03/si/sb1 p02/so/sb0 p01/sck (8) f x /2 3 f x /2 4 f x /2 6 tout0 (from timer/event counter) csim reld cmdd ackd ackt acke bsye relt cmdt dq set clr (8) (8) sbic bit test slave address register (sva) address comparator coincidence signal bit manipulation so latch bit test selec- tor selec- tor busy/ acknowledge output circuit bus release/ command/ acknowledge detection circuit serial clock counter serial clock control circuit intcsi control circuit irqcsi set signal intcsi p01 output latch serial clock selector external sck shift register (sio) 32 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 6.9 bit sequential buffer: 16 bits the bit sequential buffer (bsb) is a data memory specifically provided for bit manipulation. with this buffer, addresses and bit specifications can be sequentially updated by bit manipulation operation. therefore, this buffer is very useful for processing long data in bit units. fig. 6-9 bit sequential buffer format remarks 1. in pmem.@l addressing, bit specification is shifted according to the l register. 2. in pmem.@l addressing, the bit sequential buffer can be manipulated at any time regardless of mbe/ mbs specification. 3210321032103210 bsb3 bsb2 bsb1 bsb0 fc3h fc2h fc1h fc0h l = fh l = ch l = bh l = 8h l = 7h l = 4h l = 3h l = 0h decs l incs l address bit l register symbol 33 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 7. interrupt functions and test functions the m pd750008 has seven interrupt sources and two test sources. one test source, int2, has two types of edge detection testable input pins. the interrupt control circuit of the m pd750008 has the following functions. (1) interrupt functions ? hardware controlled vectored interrupt function which can control whether or not to accept an interrupt using the interrupt flag (ie ) and interrupt master enable flag (ime). ? the interrupt start address can be set arbitrarily. ? multiple interrupt function which can specify the priority by the interrupt priority specification register (ips) ? test function of an interrupt request flag (irq ) (the software can confirm that an interrupt occurred.) ? release of the standby mode (interrupts released by an interrupt enable flag can be selected.) (2) test functions ? whether test request flags (irq ) are issued can be checked with software. ? release of the standby mode (a test source to be released can be selected with test enable flags.) 34 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) fig. 7-1 interrupt control circuit block diagram note noise eliminator (standby release is not possible when the noise eliminator is selected.) 2 im2 14 irqbt irq4 irq0 irq1 irqcsi irqt0 irqt1 irqw irq2 intbt int4/p00 int0/p10 int1/p11 intcsi intt0 intt1 intw int2/p12 both-edge detector im0 edge detector edge detector rising edge detector falling edge detector kr0/p60 kr7/p73 selec- tor im2 interrupt enable flag (ie ) ips ist0 ime priority control circuit decoder vrqn vector table address generator standby release signal internal bus selector note im1 ist1 35 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 8. standby function the m pd750008 has two different standby modes (stop mode and halt mode) to reduce power dissipation while waiting for program execution. table 8-1 standby mode statuses notes 1. operation is possible only when the main system clock operates. 2. operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode register (im0) (when im02 = 1). instruction for setting system clock for setting clock oscillator basic interval timer/watchdog timer serial interface timer/event counter timer counter clock timer external interrupt cpu release signal halt mode halt instruction can be set either with the main system clock or the subsystem clock. only the cpu clock f stops its operation (oscillation continues). can operate only at main system clock oscillation. (irqbt is set at reference time intervals.) can operate only when external sck input is selected as the serial clock or at main system clock oscillation. can operate only when ti0 pin input is specified as the count clock or at main system clock oscillation. can operate. note 1 can operate. stop mode stop instruction can be set only when operating on the main system clock. the main system clock stops its operation. does not operate. can operate only when the external sck input is selected for the serial clock. can operate only when the ti0 pin input is selected for the count clock. does not operate. can operate when f xt is selected as the count clock. int1, int2, and int4 can operate. only int0 cannot operate. note 2 does not operate. opera- tion status item mode an interrupt request signal from hardware whose operation is enabled by the interrupt enable flag or the generation of a reset signal 36 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 9. reset function the m pd750008 is reset with the external reset signal (reset) or the reset signal received from the basic interval timer/watchdog timer. when either reset signal is input, the internal reset signal is generated. fig. 9-1 shows the configuration of the reset circuit. fig. 9-1 configuration of reset functions when the reset signal is generated, all hardware is initialized as indicated in table 9-1. fig. 9-2 shows the reset operation timing. fig. 9-2 reset operation by generation of reset signal note either of the following two values can be selected by a mask option: 2 17 /f x (21.8 ms at 6.0 mhz, 31.3 ms at 4.19 mhz) 2 15 /f x (5.46 ms at 6.0 mhz, 7.81 ms at 4.19 mhz) wdtm reset internal reset signal reset signal from basic interval timer/watchdog timer internal bus reset signal is generated operating mode or standby mode halt mode operating mode internal reset operation wait note 37 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) table 9-1 status of the hardware after a reset (1/2) program counter (pc) psw stack pointer (sp) stack bank selection register (sbs) data memory (ram) general-purpose registers (x, a, h, l, d, e, b, c) bank selection register (mbs, rbs) timer/event counter timer counter clock timer serial interface 4 low-order bits at address 0000h in program memory are set in pc bits 11 to 8, and the data at address 0001h are set in pc bits 7 to 0. 5 low-order bits at address 0000h in program memory are set in pc bits 12 to 8, and the data at address 0001h are set in pc bits 7 to 0. held 0 0 bit 6 at address 0000h in program memory is set in rbe, and bit 7 is set in mbe. undefined 1000b held held 0, 0 undefined 0 0 0 ffh 0 0, 0 0 ffh 0 0, 0 0 held 0 0 held 4 low-order bits at address 0000h in program memory are set in pc bits 11 to 8, and the data at address 0001h are set in pc bits 7 to 0. 5 low-order bits at address 0000h in program memory are set in pc bits 12 to 8, and the data at address 0001h are set in pc bits 7 to 0. undefined 0 0 bit 6 at address 0000h in program memory is set in rbe, and bit 7 is set in mbe. undefined 1000b undefined undefined 0, 0 undefined 0 0 0 ffh 0 0, 0 0 ffh 0 0, 0 0 undefined 0 0 undefined generation of a reset signal during operation generation of a reset signal in a standby mode hardware carry flag (cy) skip flags (sk0 to sk2) interrupt status flags (ist0, ist1) bank enable flags (mbe, rbe) m pd750004 m pd750006, 750008 counter (bt) mode register (btm) watchdog timer enable flag (wdtm) counter (t0) modulo register (tmod0) mode register (tm0) toe0, tout flip-flop counter (t1) modulo register (tmod1) mode register (tm1) toe1, tout flip-flop mode register (wm) shift register (sio) operation mode register (csim) sbi control register (sbic) slave address register (sva) basic interval timer/ watchdog timer 38 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) table 9-1 status of the hardware after a reset (2/2) 0 0 0 0 reset (0) 0 0 0, 0, 0 off clear (0) 0 0 undefined generation of a reset signal during operation clock generator, clock output cir- cuit interrupt digital ports processor clock control register (pcc) system clock control register (scc) clock output mode register (clom) interrupt request flag (irq ) interrupt enable flag (ie ) priority selection register (ips) int0, int1, and int2 mode registers (im0, im1, im2) output buffer output latch i/o mode registers (pmga, pmgb, pmgc) pull-up resistor specification registers (poga, pogb) generation of a reset signal in a standby mode hardware sub-oscillator control register (sos) 0 0 0 0 reset (0) 0 0 0, 0, 0 off clear (0) 0 0 held bit sequential buffers (bsb0 to bsb3) 39 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 10. mask option the m pd750008 has the following mask options: ? mask option of p40 to p43 and p50 to p53 can specify whether to incorporate the pull-up resistor. the pull-up resistor is incorporated bit by bit. the pull-up resistor is not incorporated. ? mask option of standby function can specify the wait time with the reset signal. 2 17 /f x (21.8 ms at f x = 6.0 mhz, 31.3 ms at f x = 4.19 mhz) 2 15 /f x (5.46 ms at f x = 6.0 mhz, 7.81 ms at f x = 4.19 mhz) ? mask option of subsystem clock can specify whether to enable the built-in feedback resistor. the built-in feedback resistor is enabled (it is turned on or off by software). the built-in feedback resistor is disabled (it is cut by hardware). 1 2 1 2 1 2 40 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) description representation format 11. instruction set (1) operand identifier and its descriptive method the operands are described in the operand column of each instruction according to the descriptive method for the operand format of the appropriate instructions. (for details, refer to ra75x assembler package user's manual: language (eeu-1363).) for descriptions in which alternatives exist, one element should be selected. capital letters and plus and minus signs are keywords; therefore, they should be described as they are. for immediate data, the appropriate numerical values or labels should be described. the symbols of register flags can be used as a label instead of mem, fmem, pmem, and bit. (for details, refer to m pd750008 users manual (u10740e).) however, there are some restrictions on usable labels for fmem and pmem. note only even address can be specified for 8-bit data processing. x, a, b, c, d, e, h, l x, b, c, d, e, h, l xa, bc, de, hl bc, de, hl bc, de xa, bc, de, hl, xa', bc', de', hl' bc, de, hl, xa', bc', de', hl' hl, hl+, hl-, de, dl de, dl 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label note 2-bit immediate data or label fb0h - fbfh, ff0h - fffh immediate data or label fc0h - fffh immediate data or label 0000h - 0fffh immediate data or label ( m pd750004) 0000h - 17ffh immediate data or label ( m pd750006) 0000h - 1fffh immediate data or label ( m pd750008) 0000h - 0fffh immediate data or label ( m pd750004) 0000h - 17ffh immediate data or label ( m pd750006) 0000h - 1fffh immediate data or label ( m pd750008) 12-bit immediate data or label 11-bit immediate data or label 20h - 7fh immediate data (however, bit 0 = 0) or label port0 - port8 iebt, iet0, iet1, ie0 - ie2, ie4, iecsi, iew rb0 - rb3 mb0, mb1, mb15 reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1(for mk ii mode only) caddr faddr taddr portn ie rbn mbn 41 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) (2) symbol definitions in operation description a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa' : extended register pair (xa') bc' : extended register pair (bc') de' : extended register pair (de') hl' : extended register pair (hl') pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 8) ime : interrupt master enable flag ips : interrupt priority specification register ie : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : address bit delimiter ( ) : contents addressed by h : hexadecimal data 42 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) (3) symbols used for the addressing area column remarks 1. mb indicates the memory bank that can be accessed. 2. for *2, mb = 0 regardless of mbe and mbs settings. 3. for *4 and *5, mb = 15 regardless of mbe and mbs settings. 4. for *6 to *11, each addressable area is indicated. (4) description of machine cycle column s indicates the number of machine cycles necessary for skipping any skip instruction. the value of s changes as follows: ? when no skip is performed : s = 0 ? when a 1-byte or 2-byte instruction is skipped : s = 1 ? when a 3-byte instruction note is skipped : s = 2 note 3-byte instruction: br !addr, bra !addr1, call !addr, and calla !addr1 instructions. caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle (= t cy ) of the cpu clock ( f ), and four types of times are available for selection according to the pcc setting. * 1 mb = mbe ?mbs (mbs = 0, 1, 15) * 2 mb = 0 * 3 mbe = 0 mbe = 1 : : mb = 0 (000h - 07fh), mb = 15 (f80h - fffh) mb = mbs (mbs = 0, 1, 15) * 4 mb = 15, fmem = fb0h - fbfh, ff0h - fffh * 5 mb = 15, pmem = fc0h - fffh * 6 addr = 0000h - 0fffh ( pd750004), 0000h - 17ffh ( pd750006) 0000h - 1fffh ( pd750008) m m m * 7 addr, addr1 = (current pc) - 15 to (current pc) - 1 (current pc) + 2 to (current pc) + 16 * 8 caddr = 0000h - 0fffh ( pd750004) 0000h - 0fffh (pc 12 = 0: pd750006, 750008) 1000h - 17ffh (pc 12 = 1: pd750006) 1000h - 1fffh (pc 12 = 1: pd750008) m m m * 9 faddr = 0000h - 07ffh * 10 taddr = 0020h - 007fh data memory addressing program memory addressing m mk ii mode only addr1 = m m m 0000h - 0fffh ( pd750004) 0000h - 17ffh ( pd750006) 0000h - 1fffh ( pd750008) * 11 43 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group transfer table reference mne- monic mov xch movt operand a, #n4 reg1, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @hl+ a, @hl- a, @rpa1 xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg xa, rp' reg1, a rp'1, xa a, @hl a, @hl+ a, @hl- a, @rpa1 xa, @hl a, mem xa, mem a, reg1 xa, rp' xa, @pcde xa, @pcxa xa, @bcde xa, @bcxa bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 machin- ing cycle 1 2 2 2 2 1 2 + s 2 + s 1 2 1 2 2 2 2 2 2 2 2 2 1 2 + s 2 + s 1 2 2 2 1 2 3 3 3 3 skip condition string a string a string b l = 0 l = fh l = 0 l = fh address- ing area *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *1 *1 *2 *1 *3 *3 *6 *6 operation a ? n4 reg1 ? n4 xa ? n8 hl ? n8 rp2 ? n8 a ? (hl) a ? (hl), then l ? l + 1 a ? (hl), then l ? l - 1 a ? (rpa1) xa ? (hl) (hl) ? a (hl) ? xa a ? (mem) xa ? (mem) (mem) ? a (mem) ? xa a ? reg xa ? rp' reg1 ? a rp'1 ? xa a ? (hl) a ? (hl), then l ? l + 1 a ? (hl), then l ? l - 1 a ? (rpa1) xa ? (hl) a ? (mem) xa ? (mem) a ? reg1 xa ? rp' ? m pd750004 xa ? (pc 11-8 + de) rom ? m pd750006, 750008 xa ? (pc 12-8 + de) rom ? m pd750004 xa ? (pc 11-8 + xa) rom ? m pd750006, 750008 xa ? (pc 12-8 + xa) rom xa ? (bcde) rom note xa ? (bcxa) rom note note set register b to 0 in the m pd750004. only the lsb is valid in register b in the m pd750006 and m pd750008. 44 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group bit transfer arithme- tic accumulator manipulation increment/ decrement mne- monic mov1 adds addc subs subc and or xor rorc not incs decs operand cy, fmem.bit cy, pmem.@l cy, @h+mem.bit fmem.bit, cy pmem.@l, cy @h+mem.bit, cy a, #n4 xa, #n8 a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a a reg rp1 @hl mem reg rp' bytes 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 machin- ing cycle 2 2 2 2 2 2 1 + s 2 + s 1 + s 2 + s 2 + s 1 2 2 1 + s 2 + s 2 + s 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 + s 1 + s 2 + s 2 + s 1 + s 2 + s skip condition carry carry carry carry carry borrow borrow borrow reg = 0 rp1 = 00h (hl) = 0 (mem) = 0 reg = fh rp' = ffh address- ing area *4 *5 *1 *4 *5 *1 *1 *1 *1 *1 *1 *1 *1 *1 *3 operation cy ? (fmem.bit) cy ? (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy ? (h + mem 3-0 .bit) (fmem.bit) ? cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? cy (h + mem 3-0 .bit) ? cy a ? a + n4 xa ? xa + n8 a ? a + (hl) xa ? xa + rp' rp'1 ? rp'1 + xa a, cy ? a + (hl) + cy xa, cy ? xa + rp' + cy rp'1, cy ? rp'1 + xa + cy a ? a - (hl) xa ? xa - rp' rp'1 ? rp'1 - xa a, cy ? a - (hl) - cy xa, cy ? xa - rp' - cy rp'1, cy ? rp'1 - xa - cy a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa cy ? a 0 , a 3 ? cy, a n-1 ? a n a ? a reg ? reg + 1 rp1 ? rp1 + 1 (hl) ? (hl) + 1 (mem) ? (mem) + 1 reg ? reg - 1 rp' ? rp' - 1 45 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group compari- son carry flag manipula- tion memory bit manipula- tion mne- monic ske set1 clr1 skt not1 set1 clr1 skt skf sktclr and1 or1 xor1 operand reg, #n4 @hl, #n4 a, @hl xa, @hl a, reg xa, rp' cy cy cy cy mem.bit fmem.bit pmem. @l @h+mem.bit mem.bit fmem.bit pmem. @l @h+mem.bit mem.bit fmem.bit pmem. @l @h+mem.bit mem.bit fmem.bit pmem. @l @h+mem.bit fmem.bit pmem. @l @h+mem.bit cy, fmem.bit cy, pmem. @l cy, @h+mem.bit cy, fmem.bit cy, pmem. @l cy, @h+mem.bit cy, fmem.bit cy, pmem.@l cy, @h+mem.bit bytes 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 machin- ing cycle 2 + s 2 + s 1 + s 2 + s 2 + s 2 + s 1 1 1 + s 1 2 2 2 2 2 2 2 2 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 2 2 2 2 2 2 2 2 skip condition reg = n4 (hl) = n4 a = (hl) xa = (hl) a = reg xa = rp' cy = 1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@l) = 0 (@h + mem.bit) = 0 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 address- ing area *1 *1 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 operation skip if reg = n4 skip if (hl) = n4 skip if a = (hl) skip if xa = (hl) skip if a = reg skip if xa = rp' cy ? 1 cy ? 0 skip if cy = 1 cy ? cy (mem.bit) ? 1 (fmem.bit) ? 1 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 1 (h + mem 3-0 .bit) ? 1 (mem.bit) ? 0 (fmem.bit) ? 0 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 0 (h + mem 3-0 .bit) ? 0 skip if (mem.bit) = 1 skip if (fmem.bit) = 1 skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 skip if (h + mem 3-0 .bit) = 1 skip if (mem.bit) = 0 skip if (fmem.bit) = 0 skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 0 skip if (h + mem 3-0 .bit) = 0 skip if (fmem.bit) = 1 and clear skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 and clear skip if (h + mem 3-0 .bit) = 1 and clear cy ? cy (fmem.bit) cy ? cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy ? cy (h + mem 3-0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy ? cy (h + mem 3-0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy ? cy (h + mem 3-0 .bit) 46 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group branch mne- monic br note operand addr addr1 !addr $addr $addr1 skip condition address- ing area *6 *11 *6 *7 note the shaded portion is supported in mk ii mode only. the other portions are supported in mk i mode only. bytes - - 3 1 1 machin- ing cycle - - 3 2 2 operation ? m pd750004 pc 11-0 ? addr the assembler selects the most adequate instruction from br !addr, brcb !caddr, or br $addr. ? m pd750006, 750008 pc 12-0 ? addr the assembler selects the most adequate instruction from br !addr, brcb !caddr, or br $addr. ? m pd750004 pc 11-0 ? addr1 the assembler selects the most adequate instruction from instructions below. ? br !addr ? bra !addr1 ? brcb !caddr ? br $addr1 ? m pd750006 , 750008 pc 12-0 ? addr1 the assembler selects the most adequate instruction from instructions below. ? br !addr ? bra !addr1 ? brcb !caddr ? br $addr1 ? m pd750004 pc 11-0 ? addr ? m pd750006, 750008 pc 12-0 ? addr ? m pd750004 pc 11-0 ? addr ? m pd750006, 750008 pc 12-0 ? addr ? m pd750004 pc 11-0 ? addr1 ? m pd750006, 750008 pc 12-0 ? addr1 47 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group branch subrou- tine stack control mne- monic br bra note 3 brcb calla note 3 operand pcde pcxa bcde bcxa !addr1 !caddr !addr1 bytes 2 2 2 2 3 2 3 machin- ing cycle 3 3 3 3 3 2 3 skip condition address- ing area *6 *6 *11 *8 *11 operation ? m pd750004 pc 11-0 ? pc 11-8 + de ? m pd750006, 750008 pc 12-0 ? pc 12-8 + de ? m pd750004 pc 11-0 ? pc 11-8 + xa ? m pd750006, 750008 pc 12-0 ? pc 12-8 + xa ? m pd750004 pc 11-0 ? bcde note 1 ? m pd750006, 750008 pc 12-0 ? bcde note 2 ? m pd750004 pc 11-0 ? bcxa note 1 ? m pd750006, 750008 pc 12-0 ? bcxa note 2 ? m pd750004 pc 11-0 ? addr1 ? m pd750006, 750008 pc 12-0 ? addr1 ? m pd750004 pc 11-0 ? caddr 11-0 ? m pd750006, 750008 pc 12-0 ? pc 12 + caddr 11-0 ? m pd750004 (sp - 2) ? , , mbe, rbe (sp - 6) (sp - 3) (sp - 4) ? pc 11-0 (sp - 5) ? 0, 0, 0, 0 pc 11-0 ? addr1, sp ? sp - 6 ? m pd750006, 750008 (sp - 2) ? , , mbe, rbe (sp - 6) (sp - 3) (sp - 4) ? pc 11-0 (sp - 5) ? 0, 0, 0, pc 12 pc 12-0 ? addr1, sp ? sp - 6 notes 1. set register b to 0. 2. only the lsb is valid in register b. 3. the shaded portion is supported in mk ii mode only. the other portions are supported in mk i mode only. 48 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group subrou- tine stack control mne- monic call note callf note operand !addr !faddr bytes 3 2 machin- ing cycle 3 4 2 3 skip condition address- ing area *6 *9 operation ? m pd750004 (sp - 3) ? mbe, rbe, 0, 0 (sp - 4) (sp - 1) (sp - 2) ? pc 11-0 pc 11-0 ? addr, sp ? sp - 4 ? m pd750006, 750008 (sp - 3) ? mbe, rbe, 0, pc 12 (sp - 4) (sp - 1) (sp - 2) ? pc 11-0 pc 12-0 ? addr, sp ? sp - 4 ? m pd750004 (sp - 2) ? , , mbe, rbe (sp - 6) (sp - 3) (sp - 4) ? pc 11-0 (sp - 5) ? 0, 0, 0, 0 pc 11-0 ? addr, sp ? sp - 6 ? m pd750006, 750008 (sp - 2) ? , , mbe, rbe (sp - 6) (sp - 3) (sp - 4) ? pc 11-0 (sp - 5) ? 0, 0, 0, pc 12 pc 12-0 ? addr, sp ? sp - 6 ? m pd750004 (sp - 3) ? mbe, rbe, 0, 0 (sp - 4) (sp - 1) (sp - 2) ? pc 11-0 pc 11-0 ? 0 + faddr, sp ? sp - 4 ? m pd750006, 750008 (sp - 3) ? mbe, rbe, 0, pc 12 (sp - 4) (sp - 1) (sp - 2) ? pc 11-0 pc 12-0 ? 00 + faddr, sp ? sp - 4 ? m pd750004 (sp - 2) ? , , mbe, rbe (sp - 6) (sp - 3) (sp - 4) ? pc 11-0 (sp - 5) ? 0, 0, 0, 0 pc 11-0 ? 0 + faddr, sp ? sp - 6 ? m pd750006, 750008 (sp - 2) ? , , mbe, rbe (sp - 6) (sp - 3) (sp - 4) ? pc 11-0 (sp - 5) ? 0, 0, 0, pc 12 pc 12-0 ? 00 + faddr, sp ? sp - 6 note the shaded portion is supported in mk ii mode only. the other portions are supported in mk i mode only. 49 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group subrou- tine stack control mne- monic ret note rets note operand bytes 1 1 machin- ing cycle 3 3 3 + s 3 + s skip condition uncondition address- ing area operation ? m pd750004 pc 11-0 ? (sp) (sp + 3) (sp + 2) mbe, rbe, 0, 0 ? (sp + 1), sp ? sp + 4 ? m pd750006, 750008 pc 11-0 ? (sp) (sp + 3) (sp + 2) mbe, rbe, 0, pc 12 ? (sp + 1) sp ? sp + 4 ? m pd750004 , , mbe, rbe ? (sp + 4) 0, 0, 0, 0 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 6 ? m pd750006, 750008 , , mbe, rbe ? (sp + 4) mbe, 0, 0, pc 12 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 6 ? m pd750004 mbe, rbe, 0, 0 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 then skip unconditionally ? m pd750006, 750008 mbe, rbe, 0 ? pc 12 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 then skip unconditionally ? m pd750004 0, 0, 0, 0 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) , , mbe, rbe ? (sp + 4) sp ? sp + 6 then skip unconditionally ? m pd750006, 750008 0, 0, 0, pc 12 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) , , mbe, rbe ? (sp + 4) sp ? sp + 4 then skip unconditionally note the shaded portion is supported in mk ii mode only. the other portions are supported in mk i mode only. 50 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group subrou- tine stack control interrupt control input/ output cpu control mne- monic reti note 1 push pop ei di in note 2 out note 2 halt stop nop operand rp bs rp bs ie ie a, portn xa, portn portn, a portn, xa bytes 1 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 machin- ing cycle 3 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 skip condition address- ing area operation ? m pd750004 mbe, rbe, 0, 0 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5), sp ? sp + 6 ? m pd750006, 750008 mbe, rbe, 0, pc 12 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5), sp ? sp + 6 ? m pd750004 0, 0, 0, 0 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5), sp ? sp + 6 ? m pd750006, 750008 0, 0, 0, pc 12 ? (sp + 1) pc 11-0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5), sp ? sp + 6 (sp - 1)(sp - 2) ? rp, sp ? sp - 2 (sp - 1) ? mbs, (sp - 2) ? rbs, sp ? sp - 2 rp ? (sp + 1)(sp), sp ? sp + 2 mbs ? (sp + 1), rbs ? (sp), sp ? sp + 2 ime (ips.3) ? 1 ie ? 1 ime (ips.3) ? 0 ie ? 0 a ? portn (n = 0 - 8) xa ? portn +1 ,portn (n = 4, 6) portn ? a (n = 2 - 8) portn +1 ,portn ? xa (n = 4, 6) set halt mode (pcc.2 ? 1) set stop mode (pcc.3 ? 1) no operation notes 1. the shaded portion is supported in mk ii mode only. the other portions are supported in mk i mode only. 2. when executing the in/out instruction, mbe must be set to 0 or mbe and mbs must be set to 1 and 15, respectively. 51 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group special mne- monic sel geti notes 1, 2 operand rbn mbn taddr bytes 2 2 1 machin- ing cycle 2 2 3 3 4 3 skip condition depends on the referenced instruction. depends on the referenced instruction. depends on the referenced instruction. address- ing area *10 *10 operation rbs ? n (n = 0 - 3) mbs ? n (n = 0, 1, 15) ? m pd750004 when the tbr instruction is used pc 11-0 ? (taddr) 3-0 + (taddr + 1) when the tcall instruction is used (sp - 4) (sp - 1) (sp - 2) ? pc 11-0 (sp - 3) ? mbe, rbe, 0, 0 pc 11-0 ? (taddr) 3-0 + (taddr + 1) sp ? sp - 4 when an instruction other than the tbr and tcall instructions is used execution of (taddr)(taddr + 1) instruction ? m pd750006, 750008 when the tbr instruction is used pc 12-0 ? (taddr) 4-0 + (taddr + 1) when the tcall instruction is used (sp - 4) (sp - 1) (sp - 2) ? pc 11-0 (sp - 3) ? mbe, rbe, 0, pc12 pc 12-0 ? (taddr) 4-0 + (taddr + 1) sp ? sp - 4 when an instruction other than the tbr and tcall instructions is used execution of (taddr)(taddr + 1) instruction ? m pd750004 when the tbr instruction is used pc 11-0 ? (taddr) 3-0 + (taddr + 1) when the tcall instruction is used (sp - 6) (sp - 3) (sp - 4) ? pc 11-0 (sp - 5) ? 0, 0, 0, 0 (sp - 2) ? , , mbe, rbe pc 11-0 ? (taddr) 3-0 + (taddr + 1) sp ? sp - 6 when an instruction other than the tbr and tcall instructions is used execution of (taddr)(taddr + 1) instruction notes 1. the shaded portion is supported in mk ii mode only. the other portions are supported in mk i mode only. 2. tbr and tcall instructions are assembler pseudo instructions to define tables used for geti instructions. ......................................................... ......................................................... ......................................................... ......................................................... ...................... ...................... ........................................................................ ........................................................................ ...................... 52 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) group special mne- monic geti notes 1, 2 operand taddr bytes 1 machin- ing cycle 3 4 3 skip condition depends on the referenced instruction. address- ing area *10 operation ? m pd750006, 750008 when the tbr instruction is used pc 12-0 ? (taddr) 4-0 + (taddr + 1) when the tcall instruction is used (sp - 6) (sp - 3) (sp - 4) ? pc 11-0 (sp - 5) ? 0, 0, 0, pc 12 (sp - 2) ? , , mbe, rbe pc 12-0 ? (taddr) 4-0 + (taddr + 1) sp ? sp - 6 when an instruction other than the tbr and tcall instructions is used execution of (taddr)(taddr + 1) instruction notes 1. the shaded portion is supported in mk ii mode only. 2. tbr and tcall instructions are assembler pseudo instructions to define tables used for geti instructions. ........................................................................ ........................................................................ ...................... 53 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 12. electrical characteristics absolute maximum ratings (t a = 25 c) caution absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values. capacitance (t a = 25 c, v dd = 0 v) unit v v v v v ma ma ma ma c c rated value -0.3 to +7.0 -0.3 to v dd + 0.3 -0.3 to v dd + 0.3 -0.3 to +14 -0.3 to v dd + 0.3 -10 -30 30 220 -40 to +85 -65 to +150 conditions other than ports 4 and 5 ports with a built-in pull-up resistor 4 and 5 with open drain each pin total of all pins each pin total of all pins parameter supply voltage input voltage output voltage high-level output current low-level output current operating ambient temperature storage temperature symbol v dd v i1 v i2 v o i oh i ol t a t stg parameter input capacitance output capacitance i/o capacitance symbol c in c out c io max. 15 15 15 unit pf pf pf typ. conditions f = 1 mhz 0 v for pins other than pins to be measured min. 54 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) resonator ceramic resonator crystal external clock recommended constant characteristics of the main system clock oscillator (t a = -40 to +85 c) notes 1. the oscillator frequency and x1 input frequency indicate only the oscillator characteristics. see the item of ac characteristics for the instruction execution time. 2. when the supply voltage is 2.2 v v dd < 2.7 v and the oscillator frequency is 4.7 mhz < f x 6.0 mhz, set the processor clock control register (pcc) to a value other than 0011. when the pcc is set to 0011, the time for one machine cycle cannot satisfy the defined setting of 0.85 m s. 3. the oscillation settling time means the time required for the oscillation to settle after v dd is applied or after the stop mode is released. 4. when the supply voltage is 1.8 v v dd < 2.7 v and the x1 input frequency is 4.19 mhz < fx 6.0 mhz, set the pcc to a value other than 0011. when the pcc is set to 0011, the time for one machine cycle cannot satisfy the defined setting of 0.95 m s. caution when the main system clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. ? the wiring must be as short as possible. ? other signal lines must not run in these areas. ? any line carrying a high fluctuating current must be kept away as far as possible. ? the grounding point of the capacitor of the oscillator must have the same potential as that of v ss . ? it must not be grounded to ground patterns carrying a large current. ? no signal must be taken from the oscillator. typ. parameter oscillator frequency (f x ) note 1 oscillation settling time note 3 oscillator frequency (f x ) note 1 oscillation settling time note 3 x1 input frequency (f x ) note 1 x1 input high/low level width (t xh , t xl ) min. 1.0 1.0 1.0 83.3 max. 6.0 note 2 4 6.0 note 2 10 30 6.0 note 4 500 unit mhz ms mhz ms ms mhz ns conditions v dd = 2.2 to 5.5 v after v dd reaches min. of the oscillation voltage range v dd = 2.2 to 5.5 v v dd = 4.5 to 5.5 v v dd = 2.2 to 5.5 v v dd = 1.8 to 5.5 v v dd = 1.8 to 5.5 v x1 x2 c1 c2 x1 x2 c1 c2 x1 x2 55 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) recommended constant resonator parameter khz s s khz m s unit max. typ. min. 35 2 10 100 15 32.768 1.0 32 32 5 conditions crystal external clock xt1 xt2 oscillator frequency (f xt ) note 1 oscillation settling time note 2 xt1 input frequency (f xt ) note 1 xt1 input high/low level width (t xth , t xtl ) v dd = 2.2 to 5.5 v v dd = 4.5 to 5.5 v v dd = 2.2 to 5.5 v v dd = 1.8 to 5.5 v v dd = 1.8 to 5.5 v characteristics of the subsystem clock oscillator (t a = -40 to +85 c) notes 1. the oscillator frequency and input frequency indicate only the oscillator characteristics. see the item of ac characteristics for the instruction execution time. 2. the oscillation settling time means the time required for the oscillation to settle after v dd is applied. caution when the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. ? the wiring must be as short as possible. ? other signal lines must not run in these areas. ? any line carrying a high fluctuating current must be kept away as far as possible. ? the grounding point of the capacitor of the oscillator must have the same potential as that of v ss ? it must not be grounded to ground patterns carrying a large current. ? no signal must be taken from the oscillator. when the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator. c3 c4 r xt1 xt2 56 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) recommended parameters for the oscillation circuit when a ceramic resonator is used for the main system clock (t a = -40 to +85 c) note when the csb1000j (1.0 mhz) manufactured by murata mfg. is used, a limiting resistor (rd = 4.7 k w ) is necessary (see the following figure). when one of other resonators is used, no limiting resistor is required. manufacturer product name oscillation frequency oscillation oscillation remarks (mhz) circuit constant voltage range c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. csb1000j note 1.0 100 100 2.8 5.5 rd = 4.7 k w csa2.00mg040 2.0 100 100 2.8 cst2.00mg040 incorporated incorporated 2.8 csa4.00mg 4.0 30 30 2.8 cst4.00mgw incorporated incorporated 2.8 csa4.00mgu 30 30 2.6 cst4.00mgwu incorporated incorporated 2.6 csa4.19mg 4.19 30 30 2.8 cst4.19mgw incorporated incorporated 2.8 csa4.19mgu 30 30 2.8 cst4.19mgwu incorporated incorporated 2.8 csa6.00mgu 6.0 30 30 2.9 cst6.00mgwu incorporated incorporated 2.9 csa6.00mg 30 30 2.7 cst6.00mgw incorporated incorporated 2.7 kyocera kbr-1000f/y 1.0 220 220 2.45 5.5 kbr-2.0ms 2.0 82 82 2.5 pbrc 2.00a 82 82 2.5 kbr-4.0msa 4.0 33 33 2.5 kbr-4.0mks incorporated incorporated 2.5 pbrc4.00a 33 33 2.5 pbrc4.00b incorporated incorporated 2.5 kbr-6.0msa 6.0 33 33 2.5 kbr-6.0mks incorporated incorporated 2.5 pbrc6.00a 33 33 2.5 pbrc6.00b incorporated incorporated 2.5 tdk fcr2.0m3 2.0 33 33 2.2 5.5 fcr4.0m5 4.0 15 15 2.0 fcr4.19m5 4.19 15 15 2.2 fcr6.0m5 6.0 15 15 2.5 57 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) recommended sample circuit for the main system clock when the csb1000j manufactured by murata mfg. is used when a crystal is used for the subsystem clock (t a = -10 to +60 c) caution the oscillation circuit constant and oscillation voltage range indicate the conditions to settle the oscillation, not to guarantee the accuracy of the oscillation frequency. when an accuracy oscillation frequency is needed for the implemented circuit, the oscillation frequency of the resonator should be adjusted on the circuit. ask the manufacturer of the resonator you use. manufacturer product name oscillation oscillation oscillation remarks frequency (khz) circuit constant voltage range c3 (pf) c4 (pf) r (k w ) min. (v) max. (v) daishinku dt-38 32.768 10 10 220 2.7 5.5 low-current-drain mode 2.2 5.5 low-voltage mode csb1000j x1 x2 rd c2 c1 58 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) dc characteristics (t a = -40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol ma ma v v v v v v v v v v v v v v v v v v m a m a m a m a m a m a m a m a m a m a m a m a k w k w i ol v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v oh v ol1 v ol2 i lih1 i lih2 i lih3 i lil1 i lil2 i lil3 i loh1 i loh2 i lol r l1 r l2 2.7 v v dd 5.5 v 2.2 v v dd < 2.7 v 2.7 v v dd 5.5 v 2.2 v v dd < 2.7 v 2.7 v v dd 5.5 v 2.2 v v dd < 2.7 v 2.7 v v dd 5.5 v 2.2 v v dd < 2.7 v 2.7 v v dd 5.5 v 2.2 v v dd < 2.7 v 2.7 v v dd 5.5 v 2.2 v v dd < 2.7 v 0.7v dd 0.9v dd 0.8v dd 0.9v dd 0.7v dd 0.9v dd 0.7v dd 0.9v dd v dd - 0.1 0 0 0 0 0 v dd - 0.5 50 15 i ol = 15 ma, v dd = 4.5 to 5.5 v i ol = 1.6 ma sck, so, and ports 2 to 8 v dd = 5.0 v v dd = 3.0 v 0.2 -10 -3 100 30 15 150 v dd v dd v dd v dd v dd v dd 13 13 v dd 0.3v dd 0.1v dd 0.2v dd 0.1v dd 0.1 2.0 0.4 0.2v dd 3 20 20 -3 -20 -3 -30 -27 -8 3 20 -3 200 60 min. typ. max. unit low-level output current high-level input voltage low-level input voltage high-level output voltage low-level output voltage high-level input leakage current low-level input leakage current high-level output leakage current low-level output leakage current built-in pull-up resistor ports 4 and 5 (with n-ch open drain) when the input instruction is executed with a built-in pull-up resistor with n-ch open drain each pin total of all pins ports 2, 3, and 8 ports 0, 1, 6, and 7 and reset ports 4 and 5 x1, xt1 ports 2 to 5, and 8 ports 0, 1, 6, and 7 and reset x1, xt1 sck, so, and ports 0, 2, 3, and 6 to 8 ioh = -1.0 ma sb0, sb1 n-ch open drain pull-up resistor 3 1 k w v in = v dd other than x1 and xt1 x1, xt1 v in = 13 v ports 4 and 5 (with n-ch open drain) v in = 0 v other than x1, xt1, and ports 4 and 5 x1, xt1 ports 4 and 5 (with n-ch open drain) at other than input instruction execution v out = v dd sck, so/sb0, sb1, and ports 2, 3, and 6 to 8 ports 4 and 5 (with a built-in pull-up resistor) v out = 13 v ports 4 and 5 (with n-ch open drain) v out = 0 v v in = 0 v ports 0 to 3 and 6 to 8 (except p00 pin) ports 4 and 5 (mask option) conditions 59 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) parameter power supply current note 1 min. conditions 6.0 mhz note 2 crystal c1 = c2 = 22 pf 4.19 mhz note 2 crystal c1 = c2 = 22 pf 32.768 khz note 5 crystal v dd = 5.0 v 10% v dd = 3.0 v 10 % v dd = 5.0 v 10% v dd = 3.0 v 10% v dd = 3.0 v 10% v dd = 2.5 v 10% v dd = 3.0 v, t a = 25 c v dd = 3.0 v 10% v dd = 3.0 v, t a = 25 c low-current- drain mode note 7 dc characteristics (t a = -40 to +85 c, v dd = 2.2 to 5.5 v) notes 1. this current excludes the current which flows through the built-in pull-up resistors. 2. this value applies also when the subsystem clock oscillates. 3. value when the processor clock control register (pcc) is set to 0011 and the m pd750008 is operated in the high-speed mode. 4. value when the pcc is set to 0000 and the m pd750008 is operated in the low-speed mode. 5. this value applies when the system clock control register (scc) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse. 6. mode when the sub-oscillator control register (sos) is set to 0000. 7. mode when the sos is set to 0010. 8. this value applies when the sos is set to 00 1 and the sub-oscillator feedback resistor is not used ( = dont care). symbol i dd1 i dd2 i dd1 i dd2 i dd3 i dd4 i dd5 typ. 1.9 0.4 0.72 0.27 1.5 0.25 0.7 0.23 12 7 12 6 6 8.5 5 8.5 3.5 3.5 0.05 0.02 0.02 max. 6.0 1.3 2.1 0.8 4.0 0.75 2.0 0.7 35 21 24 18 12 25 15 17 12 7 10 5 3 unit ma ma ma ma ma ma ma ma m a m a m a m a m a m a m a m a m a m a m a m a m a v dd = 5.0 v 10% note 3 v dd = 3.0 v 10% note 4 halt mode v dd = 5.0 v 10% note 3 v dd = 3.0 v 10% note 4 halt mode low-voltage mode note 6 halt mode low-volt- age mode note 6 v dd = 5.0 v 10% v dd = 3.0 v 10% low-cur- rent-drain mode note 7 xt1 = 0 v note 8 stop mode v dd = 3.0 v 10% v dd = 2.5 v 10% v dd = 3.0 v, t a = 25 c v dd = 3.0 v 10% v dd = 3.0 v, t a = 25 c t a = 25 c 60 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) ac characteristics (t a = -40 to +85 c, v dd = 2.2 to 5.5 v) cpu clock cycle time note 1 (minimum instruction execution time = 1 machine cycle) ti0 input frequency ti0 input high/low level width interrupt input high/low level width reset low level width v dd = 2.7 to 5.5 v v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v remark the shaded portion is guaranteed only when the external clock is used. when external clock is used im02 = 0 im02 = 1 notes 1. the cycle time of the cpu clock ( f ) (minimum instruction execution time) de- pends on the frequency of connected reso- nator (and external clock), the system clock control register (scc), and the proc- essor clock control register (pcc). the figure on the right side shows the cycle time t cy characteristics for the sup- ply voltage v dd during main system clock operation. 2. this value becomes 2t cy or 128/f x accord- ing to the setting of the interrupt mode register (im0). when ceramic or crystal is used operated by main system clock pulse t cy f ti t tih , t til t inth , t intl t rsl conditions min. typ. max. unit 0.67 64 m s 0.85 64 m s 0.67 64 m s 0.95 64 m s operated by subsystem clock pulse 114 122 125 m s v dd = 2.7 to 5.5 v 0 1.0 mhz 0 275 khz v dd = 2.7 to 5.5 v 0.48 m s 1.8 m s int0 note 2 m s 10 m s int1, int2, and int4 10 m s kr0 to kr7 10 m s 10 m s parameter symbol 0123456 0.5 1 2 3 4 5 6 60 64 t cy vs. v dd (main system clock in operation) operation guaranteed range 1.8 2.2 2.7 5.5 0.67 0.95 0.85 cycle time t cy [ s] m power supply voltage v dd [v] 61 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) typ. max. 250 1000 unit ns ns ns ns ns ns ns ns ns ns min. 1300 3800 t kcy1 /2 - 50 t kcy1 /2 - 150 150 500 400 600 0 0 conditions v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v r l = 1 k w v dd = 2.7 to 5.5 v c l = 100 pf note 2 symbol t kcy1 t kl1 , t kh1 t sik1 t ksi1 t kso1 parameter sck cycle time sck high/low level width si note 1 setup time (referred to sck - ) si note 1 hold time (referred to sck - ) delay time from sck to so note 1 output serial transfer operation two-wire and three-wire serial i/o modes (sck: internal clock output): (t a = -40 to +85 c, v dd = 2.2 to 5.5 v) notes 1. in two-wire serial i/o mode, so should be read as sb0 or sb1. 2. r l is the resistance of the so output line load, while c l is the capacitance. two-wire and three-wire serial i/o modes (sck: external clock input): (t a = -40 to +85 c, v dd = 2.2 to 5.5 v) notes 1. in two-wire serial i/o mode, so should be read as sb0 or sb1. 2. r l is the resistance of the so output line load, while c l is the capacitance. typ. max. 300 1000 unit ns ns ns ns ns ns ns ns ns ns min. 800 3200 400 1600 100 150 400 600 0 0 conditions v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v r l = 1 k w v dd = 2.7 to 5.5 v c l = 100 pf note 2 symbol t kcy2 t kl2 , t kh2 t sik2 t ksi2 t kso2 parameter sck cycle time sck high/low level width si note 1 setup time (referred to sck - ) si note 1 hold time (referred to sck - ) delay time from sck to so note 1 output 62 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) sbi mode (sck: internal clock output (master)): (t a = -40 to +85 c, v dd = 2.2 to 5.5 v) note r l is the resistance of the sb0/sb1 output line load, while c l is the capacitance. sbi mode (sck: external clock input (slave)): (t a = -40 to +85 c, v dd = 2.2 to 5.5 v) note r l is the resistance of the sb0/sb1 output line load, while c l is the capacitance. typ. max. 250 1000 unit ns ns ns ns ns ns ns ns ns ns ns ns ns min. 1300 3800 t kcy3 /2 - 50 t kcy3 /2 - 150 150 500 t kcy3 /2 0 0 t kcy3 t kcy3 t kcy3 t kcy3 conditions v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v r l = 1 k w v dd = 2.7 to 5.5 v c l = 100 pf note symbol t kcy3 t kl3 , t kh3 t sik3 t ksi3 t kso3 t ksb t sbk t sbl t sbh parameter sck cycle time sck high/low level width sb0/sb1 setup time (referred to sck - ) sb0/sb1 hold time (referred to sck - ) delay time from sck to sb0/sb1 output from sck - to sb0/sb1 from sb0/sb1 to sck sb0/sb1 low level width sb0/sb1 high level width typ. max. 300 1000 unit ns ns ns ns ns ns ns ns ns ns ns ns ns min. 800 3200 400 1600 100 150 t kcy4 /2 0 0 t kcy4 t kcy4 t kcy4 t kcy4 conditions v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v r l = 1 k w v dd = 2.7 to 5.5 v c l = 100 pf note symbol t kcy4 t kl4 , t kh4 t sik4 t ksi4 t kso4 t ksb t sbk t sbl t sbh parameter sck cycle time sck high/low level width sb0/sb1 setup time (referred to sck - ) sb0/sb1 hold time (referred to sck - ) delay time from sck to sb0/sb1 output from sck - to sb0/sb1 from sb0/sb1 to sck sb0/sb1 low level width sb0/sb1 high level width 63 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) v il (max.) v ih (min.) v il (max.) v ih (min.) v ol (max.) v oh (min.) v ol (max.) v oh (min.) ac timing measurement points (excluding x1 and xt1 inputs) c lock timing ti0 timing t xl t xh 1/f x x1 input v dd - 0.1 v 0.1 v t xtl t xth 1/f xt xt1 input v dd - 0.1 v 0.1 v t til t tih 1/f ti ti0 64 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) serial transfer timing three-wire serial i/o mode: two-wire serial i/o mode: t kcy1 t kcy2 t kl1 t kl2 t kh1 t kh2 t sik1 t sik2 t ksi1 t ksi2 t kso1 t kso2 sck sb0 and sb1 input data output data sck si so t kcy1 t kcy2 t sik1 t sik2 t ksi1 t ksi2 t kl1 t kl2 t kh1 t kh2 t kso1 t kso2 65 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing sck sb0 and sb1 t ksb t kl3 t kl4 t kcy3 t kcy4 t kso3 t kso4 t sbk t kh3 t kh4 t sik3 t sik4 t ksi3 t ksi4 int0, int1, int2, and int4 kr0 - kr7 t intl t inth reset t rsl sck sb0 and sb1 t ksb t sbl t sbh t sbk t kcy3 t kcy4 t kso3 t kso4 t kl3 t kl4 t kh3 t kh4 t ksi3 t ksi4 t sik3 t sik4 66 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) parameter symbol release signal setting time oscillation settling time note 1 t srel t wait note 2 note 3 release by reset release by interrupt request conditions data hold characteristics by low supply voltage in data memory stop mode (t a = -40 to +85 c) notes 1. cpu operation stop time for preventing unstable operation at the beginning of oscillation. 2. select either 2 17 /f x or 2 15 /f x with the mask option. 3. this value depends on the settings of the basic interval timer mode register (btm) shown below. data hold timing (stop mode release by reset) data hold timing (standby release signal: stop mode release by interrupt signal) - - - - 0 1 0 1 0 1 1 1 0 0 1 1 2 20 /f x (approx. 250 ms) 2 17 /f x (approx. 31.3 ms) 2 15 /f x (approx. 7.81 ms) 2 13 /f x (approx. 1.95 ms) 0 min. typ. max. unit m s ms ms 2 20 /f x (approx. 175 ms) 2 17 /f x (approx. 21.8 ms) 2 15 /f x (approx. 5.46 ms) 2 13 /f x (approx. 1.37 ms) wait time at f x = 4.19 mhz at f x = 6.0 mhz standby release signal (interrupt request) v dd t srel t wait halt mode operation mode stop instruction execution data hold mode stop mode reset v dd t srel t wait internal reset operation halt mode operation mode stop instruction execution data hold mode stop mode btm3 btm2 btm1 btm0 67 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 13. characteristic curve (reference values) i dd vs. v dd (when the main system clock is operating at 6.0 mhz with a crystal) supply voltage v dd (v) main system clock stop mode + 32 khz oscillation, and subsystem clock halt mode (sos.1 = 0) subsystem clock operating mode (sos.1 = 0) subsystem clock operating mode (sos.1 = 1) subsystem clock halt mode (sos.1 = 1) main system clock halt mode + 32 khz oscillation supply current i dd (ma) 01234567 0.001 (t a = 25 c) x1 x2 xt1 xt2 22 pf 330 k crystal 22 pf 22 pf 22 pf 6.0 mhz crystal 32.768 khz 8 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 w 68 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) i dd vs. v dd (when the main system clock is operating at 4.19 mhz with a crystal) supply voltage v dd (v) main system clock stop mode + 32 khz oscillation, and subsystem clock halt mode (sos.1 = 0) subsystem clock operating mode (sos.1 = 0) subsystem clock operating mode (sos.1 = 1) subsystem clock halt mode (sos.1 = 1) main system clock halt mode + 32 khz oscillation supply current i dd (ma) 01234567 0.001 (t a = 25 c) x1 x2 xt1 xt2 22 pf 330 k crystal 22 pf 22 pf 22 pf 4.19 mhz crystal 32.768 khz 8 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 w 69 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) i oh vs. v dd - v oh (ports 2, 3, 6, 7, and 8) i ol vs. v ol (ports 2, 3, 6, 7, and 8) 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v dd = 1.8 v v dd = 2.2 v v dd = 3 v v dd = 4 v v dd = 5.5 v v dd = 5 v v dd - v oh [v] (t a = 25 c) i oh [ma] 40 30 20 10 0 0 0.5 1.0 1.5 2.0 v dd = 1.8 v v dd = 2.2 v v dd = 3 v v dd = 4 v v dd = 5 v v dd = 5.5 v (t a = 25 c) i ol [ma] v ol [v] 70 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 14. package drawings package drawings of mass-produced products (1/2) caution the es version is different from the corresponding mass-produced products in shape and material. see "es package drawings." 44 pin plastic qfp ( 10) s44gb-80-3bs item millimeters inches n p q 0.125?.075 0.10 2.7 0.004 0.106 0.005?.003 note each lead centerline is located within 0.16 mm (0.007 inch) of its true position (t.p.) at maximum material condition. j i h n a 13.2?.2 0.520 +0.008 ?.009 b 10.0?.2 0.394 +0.008 ?.009 c 10.0?.2 0.394 +0.008 ?.009 d 13.2?.2 0.520 +0.008 ?.009 f g h 1.0 0.37 1.0 0.039 0.039 0.015 +0.003 ?.004 i j k 0.8 (t.p.) 1.6?.2 0.16 0.007 0.031 (t.p.) 0.063?.008 l 0.8?.2 0.031 +0.009 ?.008 m 0.17 0.007 +0.002 ?.003 s 3.0 max. 0.119 max. r3 3 +7 ? +0.08 ?.07 +0.06 ?.05 +7 ? detail of lead end q f g k m l r m 33 34 22 44 1 12 11 23 s p cd a b 71 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) package drawings of mass-produced products (2/2) caution the shape and material of the es version are the same as those of the corresponding mass- produced products. 42pin plastic shrink dip (600 mil) item millimeters inches a b c f g h i j k 39.13 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. 0.17 15.24 (t.p.) 5.08 max. n 0.9 min. r 1.541 max. 0.070 max. 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.600 (t.p.) 0.007 0.070 (t.p.) p42c-70-600a-1 a c d g notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. d 0.50?.10 0.020 m 0.25 0.010 +0.10 ?.05 0~15 0~15 +0.004 ?.003 +0.004 ?.005 m k n l 13.2 0.520 2) item "k" to center of leads when formed parallel. 42 1 22 21 l m r b f h j i 72 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) es package drawing 44 pin ceramic qfp for es (reference) cautions 1. find the location of pin 1 by checking the location of pin 17, which is connected to the metal cap. 2. the metal cap is connected to pin 17. the electrical level of the metal cap is v ss (gnd). 3. the lead length has not been specified because leads are cut without any detailed specifications. 2.25 11.43 8.0 1 11 12 22 23 33 34 44 11.43 8.0 0.15 0.32 0.8 (bottom) 73 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) 15. recommended soldering conditions the m pd750004, m pd750006, and m pd750008 should be soldered and mounted under the conditions recom- mended in the table below. for detail of recommended soldering conditions, refer to the information document smd surface mount technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact our sales personnel. table 15-1 surface mounting type soldering conditions m pd750004gb- -3bs-mtx : 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) m pd750006gb- -3bs-mtx : 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) m pd750008gb- -3bs-mtx : 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) m pd750004gb(a)- -3bs-mtx : 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) m pd750006gb(a)- -3bs-mtx : 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) m pd750008gb(a)- -3bs-mtx : 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) caution use of more than one soldering method should be avoided (except for partial heating method). table 15-2 insertion type soldering conditions m pd750004cu- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m pd750006cu- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m pd750008cu- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m pd750004cu(a)- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m pd750006cu(a)- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m pd750008cu(a)- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) package peak temperature: 235 c duration: 30 seconds max. (at 210 c or above) maximum allowable number of reflow processes: 3 package peak temperature: 215 c duration: 40 seconds max. (at 200 c or above) maximum allowable number of reflow processes: 3 solder bath temperature: 260 c max. duration: 10 seconds max. number of times: 1 preliminary heat temperature: 120 c max. (package surface temperature) terminal temperature: 300 c max. duration: 3 seconds max. (per device side) ir35-00-3 vp15-00-3 ws60-00-1 - infrared reflow vps wave soldering partial heating method soldering method soldering conditions soldering method soldering conditions wave soldering (terminal only) partial heating method solder bath temperature: 260 c max., duration: 10 seconds max. terminal temperature: 300 c max., duration: 3 seconds max. (for each pin) caution apply wave soldering to terminals only. see to it that the jet solder does not contact with the chip directly. symbol 74 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) appendix a functions of the m pd75008, m pd750008, and m pd75p0016 item m pd75008 m pd750008 m pd75p0016 masked rom 0000h - 1f7fh (8064 8 bits) 75x standard cpu 4 bits 8 or 8 bits 4 ? 0.95, 1.91, 15.3 m s (when operating at 4.19 mhz) not provided 000h - 0ffh 2-byte stack not available 3 machine cycles 2 machine cycles ? f , 524, 262, 65.5 khz (when the main system clock operates at 4.19 mhz) ? 2 khz one-time prom 0000h - 3fffh (16384 8 bits) (1/2) program memory data memory cpu general-purpose register when selecting the main system clock when selecting the subsys- tem clock sbs register stack area stack operation for a subroutine call instruction bra !addr1 calla !addr1 movt xa, @bcde movt xa, @bcxa br bcde br bcxa call !addr callf !faddr timer clock output (pcl) buz output (buz) 122 m s (when operating at 32.768 khz) instruction execution time 3 channels ? basic interval timer: 1 channel ? 8-bit timer/event counter: 1 channel ? clock timer: 1 channel stack instruction 000h - 1ffh (512 4 bits) masked rom 0000h - 1fffh (8192 8 bits) 75xl cpu (4 bits 8 or 8 bit 4) 4 banks ? 0.95, 1.91, 3.81, 15.3 m s (when operating at 4.19 mhz) ? 0.67, 1.33, 2.67, 10.7 m s (when operating at 6.0 mhz) provided sbs.3 = 1: mk i mode selection sbs.3 = 0: mk ii mode selection n00h - nffh (n = 0, 1) mk i mode: 2-byte stack mk ii mode: 3-byte stack mk i mode: not available mk ii mode: available available mk i mode: 3 machine cycles mk ii mode: 4 machine cycles mk i mode: 2 machine cycles mk ii mode: 3 machine cycles 4 channels ? basic interval timer/watchdog timer: 1 channel ? 8-bit timer/event counter: 1 channel ? 8-bit timer counter: 1 channel ? clock timer: 1 channel ? f , 524, 262, 65.5 khz (when the main system clock operates at 4.19 mhz) ? f , 750, 375, 93.8 khz (when the main system clock operates at 6.0 mhz) ? 2, 4, 32 khz (when the main system clock operates at 4.19 mhz) ? 2.93, 5.86, 46.9 khz (when the main system clock operates at 6.0 mhz) 75 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) item serial interface feedback resistor cut flag (sos.0) sub-oscillator current cut flag (sos.1) register bank selection register (rbs) standby release with int0 number of vectored interrupts processor clock control register power supply operating ambient temperature package m pd75008 m pd750008 m pd75p0016 3 modes are supported. ? three-wire serial i/o mode: first transferred bit switchable between the lsb and msb ? two-wire serial i/o mode ? sbi mode (2/2) can incorporate feedback resistors that are specified with the mask option. not provided not provided disable external: 3, internal: 3 available when pcc is 0, 2, or 3 v dd = 2.7 to 6.0 v incorporated incorporated provided enable external: 3, internal: 4 available when pcc is 0 to 3 v dd = 2.2 to 5.5 v sos register t a = -40 to +85 c ? 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) ? 44-pin plastic qfp (10 10 mm, 0.8 mm pitch) 76 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) appendix b development tools the following development tools are provided for the development of a system which employs the m pd750008. in the 75xl series, use the common relocatable assembler together with a device file of each model. language processors note these software products cannot use the task swap function, which is available in ms-dos ver. 5.00 or later. remark the operations of the assembler and device file are guaranteed only on the above host machines and oss. os ms-dos tm ver. 3.30 to ver. 6.2 note see " os for ibm pc ." os ms-dos ver. 3.30 to ver. 6.2 note see " os for ibm pc ." part number m s5a13df750008 m s5a10df750008 m s7b13df750008 m s7b10df750008 host machine pc-9800 series ibm pc/at and compatibles host machine pc-9800 series ibm pc/at tm and compatibles device file ra75x relocatable assembler part number m s5a13ra75x m s5a10ra75x m s7b13ra75x m s7b10ra75x distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc 77 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) prom programming tools note these software products cannot use the task swap function, which is available in ms-dos ver. 5.00 or later. remark operation of the pg-1500 controller is guaranteed only on the above host machines and oss. hardware software pg-1500 pa-75p008cu pg-1500 controller os ms-dos ver. 3.30 to ver. 6.2 note see " os for ibm pc ." host machine pc-9800 series ibm pc/at and compatibles distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hd 5.25-inch 2hc part number m s5a13pg1500 m s5a10pg1500 m s7b13pg1500 m s7b10pg1500 the pg-1500 prom programmer is used together with an accessory board and optional program adapter. it allows the user to program a single chip microcontroller containing prom from a standalone terminal or a host machine. the pg-1500 can be used to program typical 256k-bit to 4m-bit proms. the pa-75p008cu is a prom programmer adapter provided for the m pd75p0016cu/gb. it is used in conjunction with the pg-1500. this program enables the host machine to control the pg-1500 through the serial and parallel interfaces. 78 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) hardware part number m s5a13ie75x m s5a10ie75x m s7b13ie75x m s7b10ie75x distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc debugging tools the in-circuit emulators (ie-75000-r and ie-75001-r) are provided to debug programs used for the m pd750008. the system configuration is shown below. notes 1. maintenance service only 2. these software products cannot use the task swap function, which is available in ms dos ver. 5.00 or later. remarks 1. operation of the ie control program is guaranteed only on the above host machines and oss. 2. the m pd750004, m pd750006, m pd750008, and m pd75p0016 are collectively called the m pd750008 subseries. os ms-dos ver. 3.30 to ver. 6.2 note 2 see " os for ibm pc ." the ie-75000-r is an in-circuit emulator used to debug hardware and software when developing an application system using the 75x series and 75xl series. use this emulator together with optional emulation board ie-75300-r-em and emulation probe ep-75008cu-r or ep-75008g to develop application systems of the m pd750008 subseries. for efficient debugging, connect the emulator to the host machine and a prom programmer. the ie-75000-r contains emulation board ie-75000-r-em. the board is connected to the ie-75000-r. the ie-75001-r is an in-circuit emulator used to debug hardware and software when developing an application system using the 75x series and 75xl series. use this emulator together with optional emulation board ie-75300-r-em and emulation probe ep-75008cu-r or ep-75008gb-r to develop application systems of the m pd750008 subseries. for efficient debugging, connect the emulator to the host machine and a prom programmer. the ie-75300-r-em is an emulation board used to evaluate an application system using the m pd750008 subseries. use this board together with the ie-75000-r or ie-75001-r. the ep-75008cu-r is an emulation probe for the m pd750008cu. connect this emulation probe to the ie-75000-r or ie-75001-r, and the ie-75300-r- em. the ep-75008gb-r is an emulation probe for the m pd750008gb. connect this emulation probe to the ie-75000-r or ie-75001-r, and the ie-75300-r- em. a 44-pin conversion socket, the ev-9200g-44, supplied with this probe facilitates the connection of the probe to the target system. this program enables the host machine to control the ie-75000-r or ie-75001-r through the rs-232-c and centronics interface. ie-75000-r note 1 ie-75001-r ie-75300-r-em ep-75008cu-r ep-75008gb-r ie control program software ev-9200g-44 host machine pc-9800 series ibm pc/at and compatibles 79 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) os for ibm pc the following ibm pc oss are supported. os version pc dos tm ver. 3.1 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note only english version is supported. caution these software products cannot use the task swap function, which is available in ms-dos ver. 5.0 or later. 80 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) data sheet m pd75p0016 data sheet m pd750008 users manual m pd750008 instruction list 75xl series selection guide u10738e (this manual) u10328e u10740e - u10453e document number japanese english document number japanese english hardware software ie-75000-r/ie-75001-r user's manual ie-75300-r-em user's manual ep-75008cu-r user's manual ep-75008gb-r user's manual pg-1500 user's manual ra75x assembler package user's manual pg-1500 controller user's manual pc-9800 series (ms-dos) base ibm pc series (pc dos) base operation language document number japanese english c10535e c11531e c10983e - mei-1202 - ic package manual semiconductor device mounting technology manual quality grade on nec semiconductor devices reliability and quality control of nec semiconductor devices electrostatic discharge (esd) test semiconductor device quality guarantee guide microcontroller-related products guide - by third parties document name document name document name appendix c related documents some documents are preliminary editions, but they are not so specified in the tables below. documents related to devices documents related to development tools other related documents caution the above related documents are subject to change without notice. be sure to use the latest edition when you design your system. u10738j u10328j u10740j iem-5593 u10453j eeu-846 u11354j eeu-699 eeu-698 u11940j eeu-731 eeu-730 eeu-704 eeu-5008 eeu-1416 u11354e eeu-1317 eeu-1305 eeu-1335 eeu-1346 eeu-1363 eeu-1291 u10540e c10943x c10535j c11531j c10983j mem-539 c11893j u11416j 81 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconduc- tor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 82 m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8 83 pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) [memo] m pd750004, 750006, 750008, 750004(a), 750006(a), 750008(a) ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos is a trademark of ibm corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. |
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